M. MEJAIL, B.K. NESTARES, L. GRAVANO, E. TACCONI, G.R. MEIRA, A. DESAGES. Design and Performance Evaluation of a Hardware-Accelerated VLSI Architecture for Deep Neural Network Inference. Electronics, Communications, and Computing Summit, [S. l.], v. 3, n. 4, p. 19–27, 2025. Disponível em: https://eccsubmit.com/index.php/congress/article/view/227. Acesso em: 25 feb. 2026.