M. Mejail, B.K. Nestares, L. Gravano, E. Tacconi, G.R. Meira, A. Desages. “Design and Performance Evaluation of a Hardware-Accelerated VLSI Architecture for Deep Neural Network Inference”. Electronics, Communications, and Computing Summit 3, no. 4 (December 7, 2025): 19–27. Accessed February 25, 2026. https://eccsubmit.com/index.php/congress/article/view/227.