Hardware-Efficient VLSI Implementation of Post-Quantum Cryptography Primitives

Abstract

The looming disaster that quantum computing is going to be to such classical public-key cryptosystems like RSA and ECC has set the world on a quest to come up with cryptographic algorithms that are capable of resisting quantum de-cryption hence the emergence of the concept to investigate researchers on post quantum cryptography (PQC). The lattice-based algorithms in the form of the NTRUEncrypt and McEliece algorithms, and code-based have been the most prominent PQC schemes to emerge because of its sound security basis and standardization efforts by NIST. Nevertheless, they are computationally very demanding due to their naturally large key sizes and complex operations and thus finding a hardware implementation can be very challenging in energy-limited embedded and IoT applications. This paper deals with the critical necessity of efficient hardware implementations of PQC primitives by suggesting a very hardware-efficient Very Large-Scale Integration (VLSI) architecture suitable to the NTRUEncrypt and McEliece algorithms. The main key requirements are to be minimized in regard to area and power consumption as well as providing the high throughput and introducing flexibility to integrate into other security related applications. An innovative low-power design technique is used; it integrates all levels of clocks gating, operand isolation, as well as architecture-based optimization ideas; these include pipelined modular arithmetic units and hierarchical memory organization. A 28nm CMOS technology node synthesizes the proposed architecture that is described in Verilog HDL. Performance indicators are measured on the basis of gate equivalent (GE) area, power consumption, operating frequency as well as data throughput. The results have shown that up to 45 percent silicon area and 38 percent dynamic power reduction can be had over traditional, baseline implementations at the expense of little reduction in cryptographic performance. It further allows modular integration as a cryptographic co-processor with standard AMBA interfacing to allow secure realization inside RISC-V and ARM-based system-on-chip systems.These results substantiate post-quantum secure cryptographical hardware deployment across real-time embedded systems, opening the doors towards scalable ultra-low power, and future-proof secure communication networks across the post-quantum world.