Adaptive Switched Capacitor Power Gating Enabled by On Chip ML for Minimal Leakage

Abstract

The leakage power has become a major performance blocker in the extreme power-constrained System-on-Chip (SoC) implementation process, especially of always-on functionalities in Internet of Things (IoT) and edge-Artificial Intelligence (AI) apps. The traditional approaches to power gating can be quite useful in terms of reducing the power consumption in a static state, yet they tend to be not so flexible in terms of workload and environmental changes, which is necessary at real-time. In order to overcome this drawback this paper proposes an adaptive power gating architecture incorporating Switched-Capacitor-Assisted Power Gating (ScPG) and on-chip machine learning (ML) to suppress leakage more effectively. The proposed system has lightweight ML models to constantly scan the existing runtime parameters like activity level, temperature, and leakage trends and matches to dynamically tune ScPG configurations i.e., timing, capacitor engagement, and sleep signal duration. As simulated on a 28nm FD-SOI CMOS process, the proposed architecture has up to 47% leakage power savings over the conventional header-based gating architectures, and less than 5 percent area overhead and sub 50ns decision latency. These findings show that the suggested ML-based ScPG method can provide a feasible, energy-conscious substitute of power management in energy-scrimpy SoCs. The approach enables scalable context-aware power provision systems in the next-generation edge computing systems.