Implementation and Evaluation of Subthreshold Logic for Energy-Constrained IoT Devices

Abstract

The ubiquity of Internet of Things (IoT) devices has highlighted the severe importance to design circuits with ultra-low-power with specific regard to applications in a low-energy environment e.g. in battery-operated and energy-harvesting applications. Performance-efficient, basic CMOS logic-circuits tend to be inappropriate in such energy-constrained application because of excessive dynamic and stationary power requirements. Here subthreshold logic, in which transistors are driven below the threshold voltage, promises to allow significant power savings at the cost of slower switching speed. The research paper at hand is devoted to system designed and implemented low-power subthreshold logic circuits that are rational in IoT systems. We use a 65nm CMOS technology node on which to build a set of benchmark digital circuits, hypothetical elementary logic gates, adders and counters, and study their behaviour as they operate on subthreshold Vt. The design approach is related to the most important questions like sizing of the device with the help of leakage abatement and sensitivity to the process-voltage-temperature (PVT) variations. Analysis of key performance measures such as power consumption, propagation delay and power-delay product (PDP) can be simulated and hardware prototyped using industry-standard EDA tools. On experimental basis, subthreshold logic circuits have been observed to reduce power consumption by up to 90 percent, compared to super-threshold circuit designs, under typical workloads in the IoT domain, with no loss of functional correctness. These results confirm that energy-constrained embedded systems are feasible using subthreshold design and the future of improving energy-constrained embedded systems is through adaptive biasing and near-threshold techniques.