Design and Evaluation of Neuromorphic Hardware Architectures for Low-Power Edge AI Applications
Keywords:
Neuromorphic computing, Spiking Neural Networks (SNN), Edge AI, Low-power hardware, FPGA, Memristor, STDP, Event-driven processingAbstract
The paper focuses on designing and testing neuromorphic systems in hardware, and in particular those designed to perform edge AI systems with low power and real-time performance in mind. The main aim is to design Event-driven computing systems that emulate neural processes of nature to obtain energy-efficient inference at the edge. A CMOS-based and memristor-based paradigm of spiking neural network (SNN) accelerators are discussed. Leaky integrate-and-fire (LIF) neurons and leaky integrate-and-fire (LIF) neurons as well as synaptic integration instances are mapped to FPGA platforms as modular RTL implementations ready to be exploited and benchmarked in this FPGA-based prototyping workflow. Edge-relevant tasks optimal to the proposed neuromorphic cores include handwritten digit classification and dynamic vision-based gesture recognition and voice command detection. Power-performance comparing with the traditional multiply-accumulate (MAC) based AI accelerators is discussed. There are up to 70 percent dynamic power reduction and a 3x factor improvement in energy-per-inference has been observed, reflecting the architectural compatibility of SNNs to constrained edge environments. More so, this paper reviews trade-offs of on-chip learning flexibility, inversion latency, and hardware extensiveness. A deployment model at system level is proposed to provide an example of integration in the real world into edge AI stacks with emphasis on the modularity of interaction between neuromorphic processing components and embedded components. The results confirm that neuromorphic architectures bring very strong benefits to edge applications and especially in latency-, energy-, and area-sensitive applications. The scale of such a system, as well as the related design considerations, is an additional topic of interest raised in the work as it provides insight into future directions of ASIC design and adaption to hybrid edge-AI pipelines.