Design and Implementation of Secure Hardware Architectures for Real-Time Embedded Systems in Adversarial Environments
Keywords:
Secure Hardware Architecture, Real-Time Embedded Systems, Physically Unclonable Functions (PUFs), Cryptographic Coprocessors, Side-Channel Attack Mitigation, Fault Injection Resilience, Secure Boot and Authentication, FPGA-Based Prototyping Post-Quantum Cryptography, Hardware-Rooted Trust, Federated Edge Learning Security, On-Chip Anomaly Detection.Abstract
The current paper concerns a critical issue of hardware-based security of real-time embedded systems, deployed in adversarial environment, like automotive electronic control units (ECUs), industrial automation systems, and medical devices. It aims at creating and deploying a tamper-resistant, scalable, energy-efficient hardware platform that is resistant to attacks as well as maintaining the real-time performance by reducing both physical and logical attack environments. Proposed secure architecture unites the essential mechanisms such as the presence of hardware root of trust, secure bootloader, lightweight cryptographic coprocessors, and Physically Unclonable Functions (PUFs) which perform the checking in the runtime. Special interest is given to finding the balance level between a strong side of security implementation and latency, area and power limitations of an embedded platform. An FPGA-based testbed is utilized in architecture implementation and evaluation of the real-world feasibility. Any power and timing performance parameters are empirical measurable based on normal benchmarks applications executed in a simulated adversarial environment. Based on experimental results, it is shown that resistance to side-channel attacks (and among specific example here, DPA and timing analysis), memory probing and code injection is substantially increased, without any loss in the real-time responsiveness. The latency and power overhead of all the proposed systems (<10%) reveal that the suggested system would be appropriate to be deployed in an embedded environment. The paper makes a contribution of a modular and reusable design framework of hardware-secured embedded systems. Although the current realization assumes the attention to basic security primitives, the application is extended in future to post-quantum cryptography, on-chip anomaly detection based on AI, and secure federated edge-learning. Adaptability of architecture and hardware-level validation highlight the possibility of using architecture in next-generation embedded and cyber-physical systems.
