Design and Implementation of Hardware-Embedded Lightweight Cryptographic Engines for Secure IoT Edge Devices

Abstract

The proliferation of Internet of Things (IoT) devices in recent times has increased the need of gainful, real-time communication, especially in the network edge where the network source of computational and power is limited. The current paper shows the design and the implementation of hardware-based lightweight cryptographic engines that will fulfill the needs of secure IoT edge devices. The modular architecture is suggested, with a tuneable configuration of such block ciphers as the AES and PRESENT, aiming at the minimization of the logic complexity, the latency as well as the power consumption, with the aim of keeping robustness in cryptography. The architecture has been developed and synthesized on Xilinx Artix-7 and the Intel MAX10 FPGA to measure its ASIC state of readiness, synthesized using 65nm CMOS technology. Experimental findings show logic usage was reduced to 42 per cent and dynamic power consumed by 53 per cent lower than baseline software-based realizations. The energy per bit is as small as 0.67 nJ and supports sustained encryption rate greater than 500 Kbps, which means that it can be deployed into ultra-low-power applications. NIST statistical tests and side-channel analysis ensures that cryptographic standards are met and are not susceptible to leakage. These results support the potential of the offered solution to address very demanding performance and security needs of new smart city, industry and medical IoT implementations. The work provided gives a scalable and efficient cryptographic basis of next-generation edge-secure embedded systems.