2D Material-Based Tunnel FETs for Energy-Efficient Logic Switching

Abstract

Recently Tunnel field-effect transistors ( TFETs ) have been regarded as promising future candidates to design low-power, next-generation electronics, as they have the intrinsic ability to reduce their subthreshold swings below the thermionic limit of 60 mV/decade, a fundamental limit that severely limits low-power efficiency in the conventional MOSFET device. This paper explores two-dimensional (2D) material use in the TFET structures to utilize atomically thin shapes, excellent gate control, and the electronic properties that are controllable to use the materials in increased band-to-band tunneling (BTBT) efficacies. Materiaux like molybdenum disulphide (MoS 2 ), tungsten diselenide (WSe 2 ) and black phosphorus ( BP ) will be added in lateral and vertical TFET structures, and constitute an homojunction or heterojunction contact, depending on type-II or broken-gap alignment to drive the maximum efficiency in tunneling. Current performance under different working conditions and scaling will be evaluated by quantum transport simulations based on the non-equilibrium Green functions (NEGF) approach accompanied with self-consistent Poisson equations. The presented results prove that the use of 2D materials in TFETs provides substantially higher ON-current (I _ON) values without affecting their low OFF-current (I <sub>OFF</ sticks harshly contributions to being able to exceed 10 6 and as little as 25 mV/dec, respectively. Moreover, both energy-delay product and leakage power characteristics of these devices demonstrate significant performance benefits in comparison with their conventional silicon alternatives, especially in scaled supply voltages (V _DD< 0.4 V), and, thus, ultra-low-power logic and edge computing applications lie directly in their soil. An example of a case study used to adopt a 32-bit arithmetic logic unit (ALU) brings to the fore energy savings and efficiency of the system. The results make it clear that 2D TFETs have the potential to meet energy-efficient logic beyond CMOS in the International Roadmap for Devices and Systems (IRDS), and show great promise toward integration within flexible, wearable, and high density nanoelectronic systems. The paper offers a detailed review of material choice, device structure, and the trade-off between performance and costs, which highlights the paradigm-breaking opportunity of 2D semiconductors regarding the tunneling-based logic switches in the future.